Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Em

The Nile on
Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems by Filip Thoen, Francky Catthoor

system is a complex object containing a significant percentage of elec­ A tronics that interacts with the Real World (physical environments, humans, etc.

FORMAT
Hardcover LANGUAGE
English CONDITION
Brand New Publisher Description

The combination of VLSI process technology and real-time digital signal processing (DSP) has brought a break-through in information technology. This rapid technical revolution allows the integration of ever more complex systems on a single chip. However, these technology and integration advances have not been matched by an increase in design productivity, causing technology to leapfrog the design of integrated circuits (ICs). The success of these emerging "systems-on-a-chip" (SOC) can only be guaranteed by a systematic and formal design methodology, possibly automated in computer-aided design (CAD) tools, and effective re-use of existing intellectual property (IP). In this book, a contribution is made to the modelling, timing verification and analysis, and the automatic synthesis of integrated real-time DSP systems. This text gives a comprehensive overview of existing techniques. The emphasis throughout is on the support and guaranteeing of the real-time aspect and constraints of these systems, which avoids time consuming design iterations and safeguards the ever shrinking proposed "Multi-Thread Graph" (MTG) system model features two-layers, unifying a (timed) Petri net and a control-data flow graph. Its unique interface between both models offers the best of two worlds and introduces an extra abstraction level hiding the operation-level details which are unnecessary during global system exploration. The formulated timing analysis and verification approach supports the calculation of temporal separation between different MTG entities as well as realistic performance metrics for highly concurrent systems. The synthesis methodology focuses on managing the task-level concurrency (i.e. task scheduling), as part of a proposed overall system design meta flow. It emphasizes performance and timing aspects ("timeliness"), while minimizing processor cost overhead as driven by high-level cost estimators. The approach is new in the abstraction level it employs, and in its optimal hybrid dynamic/static scheduling policy which, driven by coestimators, selects the scheduling policy for each behaviour. At the low-level, RTOS synthesis generates an application-specific scheduler for the software proposed synthesis methodology (at the task-level) is asserted to yield most optimal results when employed before the hardware/software partition is made. At this level, the distinction between these two is minimal, such that all steps in the design trajectory can be shared, thereby reducing the system cost significantly and allowing tighter satisfaction of timing/performance constraints.

Table of Contents

1. Introduction.- 1. Systems-on-a-chip.- 2. Heterogeneous real-time embedded systems.- 3. Unified meta design flow for multi-media and telecom applications.- 4. Design methodology & CAD design support.- 5. Overview of the book.- 2. Related Work and Contemporary Approaches.- 1. Manual approach.- 2. Real-time operating systems.- 3. Processor architecture integration.- 4. Task concurrency management.- 5. Motivation for a new approach.- 3. System Representation Model.- 1. Model requirements.- 2. Related Work — Models considering time.- 3. Basic Multi-Thread Graph model.- 4. MTG model extended with data communication.- 5. MTG model extended with timing.- 6. MTG model extended with hierarchy.- 7. Miscellaneous extensions.- 8. Advantages of the MTG model.- 9. Future extensions.- 10. Summary.- 4. Timing Analysis.- 1. Problem formulation.- 2. Related work — Timing verification.- 3. Related work — Timing analysis.- 4. Related work — Performance analysis.- 5. MTG classification.- 6. MTG separation analysis.- 7. MTG latency and response time analysis.- 8. MTG rate analysis.- 9. MTG boundedness analysis.- 10. Summary.- 5. System Synthesis Methodology.- 1. Methodology overview.- 2. MTG model extraction.- 3. Resource estimation.- 4. Task concurrency management — Thread frame clustering.- 5. Task concurrency management — Thread frame scheduling.- 6. Task concurrency management — Execution model selection.- 7. RTOS synthesis.- 8. Summary.- 6. Conclusions.- 1. Motivation.- 2. Contributions.- 3. Future work.- Appendices.- Definitions.- 1. Multi-sets.- 2. MTG definitions and properties.- 2.1 Definitions.- 2.2 Behavioral and structural properties.- 3. Algebras.- 3.1 Number algebras.- 4. Relations and partial orders.- 4.1 Binary relations.- 4.2 Partial orders.- 5. Automata.

Promotional

Springer Book Archives

Long Description

system is a complex object containing a significant percentage of elec

Details ISBN0792377370 Year 1999 ISBN-10 0792377370 ISBN-13 9780792377375 Format Hardcover Place of Publication Dordrecht Edited by Francky Catthoor DEWEY 004.33 Birth 1959 Affiliation IMEC, Leuven, Belgium Author Francky Catthoor Media Book Short Title MODELING VERIFICATION & EXPLOR Language English Publication Date 1999-11-30 Pages 438 Edition 2000th Illustrations XV, 438 p. DOI Alternative 9781461369981 Audience Postgraduate, Research & Scholarly Edition Description 2000 ed. Country of Origin US Product Class Description Computing: Professional & Programming Publisher Kluwer Academic Publishers Imprint Kluwer Academic Publishers Country of Publication United States US Release Date 1999-11-30
We\'ve got this

At The Nile, if you\'re looking for it, we\'ve got it.
With fast shipping, low prices, friendly service and well over a million items - you\'re bound to find what you want, at a price you\'ll love!

TheNile_Item_ID:96222489;